VLSI System Verilog (48 Hours)

What’s the course about

VLSI systems are designed using hardware description languages (HDLs). There are three types of HDLs: VHDL, Verilog, and System Verilog. VHDL and Verilog are considered a general-purpose digital design language, and System Verilog is an enhanced version of Verilog.

These HDLs are not software programming languages but the ones that describe propagation time and signal strengths - in short the behavior of electronic circuits or products. System Verilog combines HDLs and a hardware verification language. It takes an object-oriented programming approach.

Course objectives

System Verilog combines HDLs and a hardware verification language. It takes an object-oriented programming approach. It also teaches how to code in system Verilog language-which is the most popular Hardware description language used for SoC design and verification in semiconductor industry.

Key course content

• Pre-defined and User defined data types
• Array types (Static, dynamic, associative)
• OOPs programming concepts (Eg: Class, Inheritance)
• Constrained random stimulus generation
• Casting (Static & dynamic)
• SV Schedulers
• Inter Process communication (Semaphore, mailbox)
• Coverage Analysis (Code, Functional, FSM)
• Interfaces and clocking block
• Test bench creation using system Verilog concepts

Who can enroll

Electrical and electronics students, IT students, and anyone with a background of C or C++ or any Object-Oriented programming language can enroll for the program.

Job opportunities

Students can apply for some of the following jobs: Design Verification Engineer, System Level Verification Engineer, ASIC Verification Engineer, VLSI Verification Engineer, Design Verification Engineer and Functional Verification Application Engineer. These job openings are available usually at companies manufacturing semiconductors, electronic products and IT hardware.